Conventional multi-processor systems adapted to transmit data between a processor A and a processor B have a dual port memory (hereinafter referred to as the "DPM") which is a common memory accessible from both the processors A and B as desired for the transmission of data between the processors (Japanese Laid-Open Patent Application No. 62-242268).
The DPM has the function of generating an interrupt signal for one of the processors in response to an interrupt request signal from the other processor.
The interrupt request to be made by the processor A for the processor A to communicate with the processor B is accomplished by the processor A by writing data at a specified address in the DPM. Upon the processor A writing the data at the specified address, the control circuit of the DPM, monitoring address signals from both the processors, feeds an interrupt signal to the processor B for the request of interrupt. Upon accepting the interrupt signal, the processor B performs its interrupt processing routine to read out the data from the address in the DPM.
However, the method employed by the conventional multi-processor system for detecting the malfunction of the DPM is merely such that one of the processors, when writing the specified data in the DPM, reads out the stored data to check whether it is identical with the specified data. Accordingly, despite the interrupt request made by the processor, the other processor is unable to recognize the request in the event of malfunctioning of the DPM. Further if the interrupt signal generating function of the DPM has failed, the DPM and both the processors are unable to check whether this function is faulty. Thus, the conventional system requires considerable time for trouble-shooting.